| Patent Title | Method and Analysis of computer aided CMOS based analog circuit design |
| Department | Electronics and Comminications |
| Year | 2025 |
| Faculty Name | Pankaj Prajapati |
| Status | Published |
| Abstract | This invention presents an automated methodology for sizing and optimizing CMOS-based analog circuits using a hybrid metaheuristic approach that combines the global exploration strengths of the Cuckoo Search (CS) algorithm with the local exploitation capabilities of Particle Swarm Optimization (PSO), forming a hybrid CSPSO algorithm. Analog circuit design, particularly in mixed-signal System-on-Chip (SoC) environments, remains a time-consuming challenge due to its nonlinear nature, sensitivity to process-voltage-temperature (PVT) variations, and lack of mature automation tools compared to digital design. To address this, the proposed method integrates CS and CSPSO algorithms within a Computer-Aided Design (CAD) framework, coded in C and interfaced with SPICE simulation in a Linux environment. The framework automates the optimization of essential analog building blocks?such as current mirrors, amplifiers, voltage-controlled oscillators (VCOs), and operational transconductance amplifiers (OTAs)?in 0.18 ?m and 0.35 ?m CMOS technologies. The optimization process begins with algorithm initialization, generating a population of potential solutions (nests), followed by evaluation through SPICE simulations using a fitness function based on normalized root mean square error between target and simulated specifications. The hybrid CSPSO algorithm alternates between CS-driven L?vy flight explorations and PSO-based refinements to efficiently search the design space, updating and selecting |